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datasheet february 2004 1/49 stv9937 120-mhz on-screen display for monitors including pictureboost tm and 4 true independent window displays ? main features horizontal frequency up to 150 khz i2c interface for microcontrollers with slave address ba(h) in read and write modes pictureboost pixel clock (f pixel1 ) for the pictureboost (pb) from 30 to 60 mhz synchronised either on hsync or on hfly: clk1 window position programmable by rgb or i 2 c interface video analog inputs with comparator on three channels three 8 bit registers for other data, programmable by rgb osd on-chip pixel clock generator (f pixel2 ) from 7.68 mhz to 120 mhz, clk2 osd clock synchronized on hsync or hfly programmable horizontal resolutions from 384 to 1524 dots per scan line 4 independent windows all with character display overlapping windows with automatic control of display priorities and scrolling menu effects independent and programmable displays, positions and sizes for each window transparent or 8 programmable background colors for each window window size up to 16 rows of 32 characters each window has its own bordering or shadowing effects with programmable color, height and width each window can be separately erased programmable common positioning to easily control centered display 496 standard and 16 multi-color characters or graphic fonts in rom. character fonts can be customized using a mask-programmable rom characters common character height and row space. character height from 18 to 127 lines and space lines from 0 to 62 split above and below character rows 12 x 18 dot matrix per character display of up to 640 characters programmable shadow effects for characters in each separate window 32 programmable background, foreground, blinking character colors for characters (8 possibilities per window) 8 selectable colors for standard characters transparent and 8 selectable colors for background on-screen effects fade-in/fade-out effects possibility of full-screen display with a selectable color pdip 24 (plastic dual in line shrink package) order code: stv9937p/aa
stv9937 2/49 chapter 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 pin description .......................................................................................................... ......... 7 chapter 2 register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.1 i2c protocol ............................................................................................................... ........... 9 2.1.1 data to write ............................................................................................................ .............................................9 2.1.2 transmission formats ..................................................................................................... ......................................9 2.1.3 format, window and row address (fwr) ..................................................................................... ....................10 2.1.4 format, attribute and column address (fac) ............................................................................... .....................10 2.1.5 control data, color codes or character codes ............................................................................. ....................11 2.1.6 configuration of transmission formats ................................................................................... ..........................11 2.2 format changing ............................................................................................................ ... 11 to change from format a to format b ........................................................................................... ....................11 to change from format a to format c ........................................................................................... ....................11 to change from format b to format a ........................................................................................... ....................11 to change from format b to format c ........................................................................................... ....................12 2.3 read mode .................................................................................................................. ....... 12 2.4 addressing map ............................................................................................................. .... 12 chapter 3 window specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.1 enable display ............................................................................................................. ...... 14 3.2 origin positions for the 4 windows .................................................................................... 14 3.2.1 general horizontal delay (hd) ............................................................................................ ...............................14 3.2.2 general vertical delay (vd) .............................................................................................. ..................................14 3.3 window positions in the frame .......................................................................................... 15 3.3.1 window horizontal delay .................................................................................................. ..................................15 3.3.2 window vertical delay .................................................................................................... ....................................15 3.4 window size: number of character rows and character columns .................................. 16 3.4.1 window horizontal size ................................................................................................... ...................................16 3.4.2 window vertical size ..................................................................................................... .....................................16 3.5 window background color ................................................................................................. 17 3.6 window bordering and shadowing effects ........................................................................ 17 3.6.1 enable bordering or shadowing effects .................................................................................... .........................17 3.6.2 bordering or shadowing selection ......................................................................................... ............................17 3.6.3 border or shadow color ................................................................................................... ..................................18 3.6.4 bordering or shadowing size .............................................................................................. ...............................18 3.7 window display priority management ............................................................................... 19 chapter 4 character specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.1 general description ........................................................................................................ ... 20 4.2 horizontal resolution ..................................................................................................... ... 20 4.3 character height .......................................................................................................... ..... 20
3/49 stv9937 4.4 space lines ................................................................................................................ ....... 21 4.5 character colors ........................................................................................................... ..... 22 4.5.1 character background color ............................................................................................... ...............................22 4.5.2 character color .......................................................................................................... .........................................23 4.5.3 character blinking effect ................................................................................................ ....................................24 4.6 character shadowing ........................................................................................................ .24 4.7 character font ............................................................................................................. ...... 25 chapter 5 ram specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 5.1 character coding ........................................................................................................... .... 26 5.2 window memory allocation ................................................................................................ 26 5.3 memory size allocation ..................................................................................................... .26 5.4 window reset ............................................................................................................... ..... 28 chapter 6 pixel clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 chapter 7 picture boosttm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 7.1 video rgb input stage ...................................................................................................... 30 7.2 pictureboosttm rgb decoder ........................................................................................ 31 7.2.1 data sent using i2c ...................................................................................................... ......................................31 7.2.2 data sent using the rgb channel .......................................................................................... ..........................31 7.3 control registers description ............................................................................................ 33 7.4 line and pixel offsets ..................................................................................................... ... 34 7.5 pll synchronised ........................................................................................................... ... 34 chapter 8 general osd programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 8.1 enable osd ................................................................................................................. ...... 35 8.2 fade-in and fade-out effect .............................................................................................. 35 8.3 full screen display ........................................................................................................ .... 35 8.4 signal polarity and triggering ........................................................................................... 3 6 vertical sync triggering (vs input) ........................................................................................... ..........................36 horizontal sync triggering (hsync input) ...................................................................................... ...................36 rgb output polarity (rout, gout and bout outputs) ............................................................................. ......36 fast blanking output polarity (fblk output) ................................................................................... ...................37 8.5 reset ...................................................................................................................... ............ 37 power on reset ................................................................................................................ .................................37 soft reset .................................................................................................................... .......................................37 pll register reset ............................................................................................................ .................................37 chapter 9 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
stv9937 4/49 9.1 register specification ..................................................................................................... ... 38 chapter 10 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2 10.1 software hints ............................................................................................................ ........ 42 10.1.1 programming recommendations ............................................................................................. ..........................42 10.1.2 examples of programming ................................................................................................. .................................42 hard reset at power-up (following a power-up) ................................................................................. ..................42 change of position & size of 1 window (ex. window 3) without disable of window .............................................42 re-allocation, reset, and writing new characters in windows ................................................................... ...........43 10.2 hardware hints ............................................................................................................ ...... 43 chapter 11 application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 chapter 12 electrical and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 12.1 absolute maximum ratings ............................................................................................... 45 12.2 operating conditions ...................................................................................................... ... 45 12.3 electrical and timing characteristics ................................................................................. 45 12.4 i2c bus characteristics ................................................................................................... ... 46 chapter 13 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 chapter 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 8
5/49 stv9937 general description 1 general description the stv9937 is an advanced on screen display generator for crt monitors. it includes a specific architecture allowing multiple menu displays, a built in 512 character rom and the picture boost tm system. the patented picture boost tm feature allows images to be boosted either within a window, a screen area or even over the entire screen. using traditional architecture (osd + preamp stv9212) and without any additional devices on the crt board, picture boost tm boosts the brightness and sharpness of the video on crt displays giving a tv like effect. the stv9937 can drive picture boost tm either through the vga cable (using rgb or ddc), through the usb channel via the mcu or through the osd menu (the registers can be accessed by the mcu via i2c). the stv9937 embeds the rgb data decoder, the picture boost tm control registers and the picture boost tm signal generator. along with the picture boost tm and traditional osd features, the stv9937 allows a simultaneous display of up to four menus anywhere on the screen. each of the four independent windows, all displaying characters, can be overlapped and display priorities are automatically controlled. window sizes and positions are independently programmable as well as scrolling menu effects. programming of the general osd and of the 4 windows is controlled by an i2c bus in read and write modes, to suit the various crt displays. associated with an easily programmable character height, the internal pll generates the programmable pixel clock, without using a crystal oscillator, that defines the character width making the device suitable for multi-sync applications. a maximum of 640 characters, defined in the mask-programmable rom, are distributed among the 4 windows and displayed simultaneously. figure 1: multi-window concept with character display
general description stv9937 6/49 figure 2: stv9937 block diagram figure 3: pictureboost tm system block diagram rin gin bin sda scl hsync hfly vs rp vco test1 test2 rgb input buffer picture boost tm decoder and generator osd sequencer pb sequencer pll reset reset signals ram rom osd generator 4 windows i2c interface and registers test osd pixel clock pb pixel clock pb rout stv9937 gout bout fblk stv9937 h sync osd: stv9937 video amplifier ac or dc picture boost ? window ? software picture boost ? window ? software r g b boost osd fblk preamplifier: stv9212 computer main unit monitor crt board pictureboost ? window coordinate register decoder video card ddc h sync v sync d i p 2 4 s d i p 2 4 pictureboost? color code boost gain & sharpness contrast contrast drive drive i2c line pll line pll h fly osd generator osd generator
7/49 stv9937 general description 1.1 pin description figure 4: pin connections table 1: pin descriptions n pin name direction digital/analog function 1 avss - supply analog ground 2 rp i/o analog for vco 3 vco i/o analog for vco 4 avdd - supply analog power supply 5 test1 input digital remains at 0 (for test purposes only) 6 test2 input digital remains at 0 (for test purposes only) 7 hfly input digital horizontal flyback input 8 vs input digital vertical synchronization input 9 hsync input digital horizontal synchronization input 10 sda i/o digital serial data of i2c bus 11 scl input digital serial clock of i2c bus 11 dvdd - supply digital power supply 12 n/c - - - 13 fblk output digital fast blanking output 14 rout output digital osd red color output 15 gout output digital osd green color output 16 bout output digital osd blue color output 17 pb output digital pictureboost tm output 18 dvss - supply digital ground ivss bin gin rin ivdd dvdd dvss pb bout gout rout fblk avss rp vco avdd test1 test2 hfly vs hsync sda scl 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
general description stv9937 8/49 19 dvdd - supply digital power supply 20 ivdd - supply power supply for video input 21 rin input analog vga signal input, red channel 22 gin input analog vga signal input, green channel 23 bin input analog vga signal input, blue channel 24 ivss - supply ground for video input table 1: pin descriptions (continued) n pin name direction digital/analog function
9/49 stv9937 register addressing 2 register addressing all osd control registers are located in window 0, row 0. pictureboost tm control registers are located in window 0, row 1. all color-boxes data are located in window 0, row 2. three formats are available: a, b and c, as described in the i2c protocol (see section 2.1: i2c protocol ). all addresses (fac and fwr bytes) are based on formats a or b, and are written in hexadecimal format. 2.1 i2c protocol the serial interface with the microcontroller is an i2c bus with 2 wires: scl and sda.the osd is a slave circuit with 2 modes: write and read. the slave address of the osd is bah in write mode and bbh in read mode. 2.1.1 data to write in the osd, the i2c bus is used to write - read: the control data the character codes and their respective color codes the color-boxes (8 color-boxes per window). a color-box contains the character color, character background color and blink data. there are 8 color-boxes for each osd window which are used to define the colors available for all the characters of the given osd window. 3 bits are required to code the 8 color-boxes. these bits are the color code. for more information, refer to section 4.5: character colors on page 22 . each character code is related to its own window, row and column. consequently, the protocol of the i2c transmission includes this information (window, row and column) to define the position of the character on the screen. these 3 pieces of information about the position are transmitted in 2 bytes. as each character on the screen has its own color code, the same protocol is used to write all the color codes and character codes. only the attribute bit called ?a? allows the character codes to be distinguished from the color codes corresponding to one position on the screen. the control data is also written with the same protocol using windows, rows and columns. window 0 is reserved for control data and color codes. 2.1.2 transmission formats there are 3 transmission formats to suit the amount of data to update. the transmission format is coded in the ?window/row/column? bytes. format a is suitable for updating small amounts of data which are allocated to different window, row and column addresses. format b is recommended for updating data for the same window and the same row address, but with a different column address and when changing the character/color-box attribute (bit a), or when writing to a different i2c control register. format c is appropriate for updating large amounts of data from a full window or full screen. the window, row and column addresses are incremented automatically when this format is applied. data is written to fill all the allocation memory of the windows.
register addressing stv9937 10/49 the transmission formats are as follows: 1. format a: s-fwr-fac-d fwr-fac-d fwr-fac-d fwr-fac-d...stop 2. format b: s-fwr-fac-d fac-d fac-d fac-d...stop 3. format c: s-fwr-fac-d d d d...stop where: s = slave address = bah fwr = format, window and row address fac = format, attribute and column address d = ctrl control data (8 bits), cb color codes (3 bits) or rc character codes (9 bits). in format c, the order of automatic incrementation for data d is first the column value, then the row value, and then the window value. 2.1.3 format, window and row address (fwr) bit 7 indicates the ?window & row? byte when set to 1. w[2:0] : window number 000: control data and color codes 001: window 1 010: window 2 011: window 3 100: window 4 r[3:0] : row numbers from 0 to 15. each window has a maximum number of 16 rows. 2.1.4 format, attribute and column address (fac) bit 7 indicates the ?attribute & column? byte when set to 0. f : format 0: format a or b 1: format c a: transmission of character code or color code 0: character code 1: color code and character code msb when reading or writing control data and/or character codes, bit a must be set to 0. for color code and character code msb, bit a must be set to 1. table 2: various bytes coded in the i2c transmission byte bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fwr 1 w[2:0] r[3:0] fac 0 f a c[4:0] d : control data (in window 0 only) ctrl[7:0] d : color code and character code msb 0 0 0 rc[8] 0 cb[2:0] d : character code lsbs rc[7:0]
11/49 stv9937 register addressing c[4:0] : column number there are 32 possible columns. 00000: 1 column 11111: 32 columns 2.1.5 control data, color codes or character codes color codes are stored on 3 bits. control data is stored on 8 bits and character codes are stored on 9 bits. 2.1.6 configuration of transmission formats all formats must start with the s, fwr and fac bytes. 2.2 format changing to change from format a to format b s-fwr[0]- fac[0]-d[0] fwr[1]- fac[1]- d[1] fwr[2]- fac[2]- d[2] fac[3]- d[3] fac[4]- d[4] fac[5]- d[5]... the f bit from the fac byte is always 0 in this case. to change from format a to format c s - fwr[0]- fac[0]- d[0] fwr[1]- fac[1]- d[1] fwr[2]- fac[2]- d[2] d[3] d[4] d[5]... the ?f? bit from the fac byte is as follows: f[0] = f[1] = ?0? f[2] = ?1? to change from format b to format a s - fwr[0]- fac[0]-d[0] fac[1]- d[1] fac[2]-d[2] fwr[3]- fac[3]- d[3] fwr[4]- fac[4]- d[4]... the f bit from the fac byte is always 0 in this case. table 3: configuration of transmission formats byte format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address bytes for characters codes windows & rows fwr a, b or c 1 w[2:0] r[3:0] column (a and b) fac a or b 0 0 0 c[4:0] column (c) fac c 0 1 0 c[4:0] address bytes for color codes windows & rows fwr a, b or c 1 w[2:0] r[3:0] column (a and b) fac a or b 0 0 1 c[4:0] column (c) fac c 0 1 1 c[4:0]
register addressing stv9937 12/49 to change from format b to format c s - fwr[0]- fac[0]- d[0] fac[1]- d[1] fac[2]- d[2] d[3] d[4]... the ?f? bit from the fac byte is as follows: f[0] = f[1] = ?0? and f[2] = ?1? it is not possible to change from format c back to format a or b. 2.3 read mode the transmission format is shown as below: start - s(w) - fwr- fac - stop - start - s(r) - d d d d...stop where: s(w) = slave address in write mode = bah = 10111010, s(r) = slave address in read mode = bbh = 10111011. registers and data in ram are readable. this mode is useful when developing osd applications. 2.4 addressing map figure 5: format changing sequences table 4: window addressing map window row column data window 0 row 0 columns 0 to 31 control data (8 bits) window 0 row 1 columns 0 to 31 pictureboost tm data window 0 row 2 columns 0 to 31 color-boxes (8 bits) windows 1, 2, 3 and 4 rows 0 to n (n = 15 max.) columns 0 to m (m = 31 max.) characters coding (12 bits) start format a start format c format b
13/49 stv9937 window specifications 3 window specifications four different independent windows with separate character displays can be simultaneously displayed on screen. it is possible to have overlapping windows with an automatic control of display priorities: downscale priorities from window 4 to window 1. window 1 is well-adapted for the osd general menu. the 4 windows, each with its own character display, can be positioned anywhere on the screen. the following characteristics are defined for each window: enable display position size, adjustable with memory allocation background color bordering or shadowing effects with programmable color, height and width. figure 6: example of window displays screen window 1 window 2 window 3 window 4 axis hd vd origin
window specifications stv9937 14/49 3.1 enable display the enable display command for each window is selected by bits enw1, enw2, enw3 and enw4. if the enwi bit is set to 1, the corresponding window is displayed. 3.2 origin positions for the 4 windows the 4 windows are arranged in a frame whose origin coordinates are the horizontal delay (hd) and the vertical delay (vd) located at the upper left-hand corner of the monitor screen. when the hd and vd values are changed, the 4 windows within the frame position are automatically shifted by the same value. the origin (hd, vd) can be programmed anywhere on the screen. adjusting the origin position is used to globally reposition the osd windows. the advantages of this system are easier programming, the possibility to adapt the position of all windows at a single time without changing the relative position of each window and the possibility for the user to program all 4 window positions. 3.2.1 general horizontal delay (hd) the general horizontal delay defines the horizontal position of the origin coordinate for all four osd windows. the horizontal delay is selected by bits hd[6:0]. general horizontal offset = 50 pixels general horizontal delay = hd[6:0] x 6 pixels + general offset (in pixels) the default value of the horizontal delay is 0h (left-hand side of the monitor screen). 3.2.2 general vertical delay (vd) the general vertical delay defines the vertical position of the origin coordinate for all four osd windows. the vertical delay is selected by bits vd[7:0]. a general vertical offset of 2 scan lines is also applied. the range of the vertical delay is from 2 to 1022 scan lines, in steps of 4 scan lines each. general vertical delay = vd[7:0] x 4 + 2 (in scan lines) the default value of the vertical delay is 0h (top of screen). table 5: enable display fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 07h 0h enw4 enw3 enw2 enw1 table 6: origin of windows on horizontal axis: horizontal delay fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 04h 0h hd[6:0] table 7: origin of windows on vertical axis: vertical delay fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 05h 0h vd[7:0]
15/49 stv9937 window specifications 3.3 window positions in the frame all values are referenced to the origin coordinates (hd, vd). for more information, refer to figure 6 on page 13 . 3.3.1 window horizontal delay the window horizontal delay defines the horizontal start position for each separate osd window. this value is selected by bits hdw1[6:0], hdw2[6:0], hdw3[6:0] and hdw4[6:0], respectively. the range of the window horizontal delay is from 0 to 1524 pixels, in steps of 12 pixels each. window horizontal delay = hdwi[6:0] x 12 pixels the total horizontal delay of a window is: general horizontal delay + hdwi[6:0] x 12 pixels; or, hd[6:0] x 6 pixels + hdwi[6:0] x 12 pixels + (50 pixels). the default values for the window horizontal delay for each of the four osd windows is given in ta bl e 8 . 3.3.2 window vertical delay the window vertical delay defines the vertical start position for each separate osd window. this value is selected by bits vdw1[5:0], vdw2[5:0], vdw3[5:0] and vdw4[5:0], respectively. the range of the window vertical delay is from 0 to 63 rows of characters, in steps of 1 character row each. it is important to note that the height of each character row is defined by the row height parameter. for more information, refer to section 4.4: space lines on page 21 . window vertical delay = vdwi[5:0] x row_height the total vertical delay of a window is: general vertical delay + vdwi[5:0] x row_height (in scan lines); or, (vd[7:0] x 4 + 2) + vdwi[5:0] x row_height (in scan lines). the default values for the window vertical delay for each of the four osd windows is given in ta bl e 9 . table 8: window horizontal delay fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 0ch, 11h, 16h, 1bh 0h, 20h, 0h, 10h hdwi[6:0] table 9: window vertical delay fwr fac default bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 80h 0dh, 12h, 17h, 1ch 0h, 0h, ch, ch vdwi[5:0]
window specifications stv9937 16/49 3.4 window size: number of character rows and character columns 3.4.1 window horizontal size the window horizontal size defines the number of characters displayed for character row for each separate osd window. this value is selected by bits hsw1[4:0], hsw2[4:0], hsw3[4:0] and hsw4[4:0], respectively. the range of the window horizontal size is from 1 to 32 characters, in steps of 1 character each. each character is 12 pixels long. there is an offset of 1 character. window horizontal size = hswi[4:0] +1 characters the default values for the window horizontal size for each of the four osd windows is given in ta bl e 1 0 . 3.4.2 window vertical size the window vertical size defines the number of character rows displayed for each separate osd window. this value is selected by bits vsw1[3:0], vsw2[3:0], vsw3[3:0] and vsw4[3:0], respectively. the range of the window vertical size is from 1 to 16 character rows, in steps of 1 character row each. it is important to note that the height of each character row is defined by the row height parameter. for more information, refer to section 4.4: space lines on page 21 . there is an offset of 1 character row. window vertical size = (vswi[3:0] + 1) x row_height (in scan lines) row_height = character_height + 2 x space_lines the default values for the window vertical size for each of the four osd windows is given in ta bl e 1 1 . ta bl e 1 2 shows an example of the origin and size of windows based on the example shown in figure 8 , table 10: window horizontal size fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 0eh, 13h, 18h, 1dh 19h, 9h, fh, fh hswi[4:0] table 11: window vertical size fwr fac default bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 80h 0fh, 14h, 19h, 1eh bh, 4h, 7h, 7h vswi[3:0] table 12: example of origin and size of windows window i hd vd hswi vswi window 1 0274 window 2 5045
17/49 stv9937 window specifications 3.5 window background color the window background color for each separate osd window is coded over 4 bits as shown in ta bl e 1 3 . the first bit (ti) specifies whether the background is transparent or if a color is displayed. if the background is transparent (ti = 1), the active video is displayed as background. if a color is displayed (ti = 0), the background color for each separate osd window is coded over the last three bits (rwi, gwi and bwi, respectively). windows are displayed with a white background by default (7h). 3.6 window bordering and shadowing effects 3.6.1 enable bordering or shadowing effects bordering or shadowing effects are enabled for each separate osd window by bits enbs1, enbs2, enbs3 and enbs4, respectively. 3.6.2 bordering or shadowing selection either the bordering or the shadowing effect is selected for each separate osd window by bits bsw1, bsw2, bsw3 and bsw4, respectively. window 3 6463 window 4 3744 table 13: background color of each window fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 10h, 15h 1ah, 1fh 7h, 7h, 7h, 7h ti rwi gwi bwi table 14: bordering and shadowing parameter selection bit description enbsi 0: no bordering, no shadowing (default value) 1: bordering or shadowing is selected. bswi 0: bordering is selected (default value) 1: shadowing is selected. table 15: enable bordering or shadowing effects fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 07h 0h enbs4 enbs3 enbs2 enbs1 80h 10h, 15h 1ah, 1fh 0h, 0h, 0h, 0h bswi table 12: example of origin and size of windows window i hd vd hswi vswi
window specifications stv9937 18/49 3.6.3 border or shadow color the border or shadow color is separately programmable for each separate osd window. this value is selected by bits wsri, wsgi and wsbi for each of the four osd windows. the value for each color is shown in table 17 . 3.6.4 bordering or shadowing size the size of the bordering or shadowing width is separately programmable for each separate osd window. this value is selected by bits bswwi[2:0] for each of the four osd windows. the width size is from 0 to 14 pixels, in steps of 2 pixels each. width size = bswwi[2:0] x 2 pixels the size of the bordering or shadowing height is selected by bits bshwi[3:0] for each of the four windows. the height size is from 0 to 30 lines, in steps of 2 scan lines each. height size = bshwi[3:0] x 2 scan lines. table 16: border or shadow color fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 10h, 15h 1ah, 1fh 0h, 0h, 0h, 0h wsri wsgi wsbi table 17: bordering and shadowing color selection (wsrgbi) value color value color 000 black (default) 100 red 001 blue 101 magenta 010 green 110 yellow 011 cyan 111 white table 18: bordering or shadowing size fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 0eh, 13h 18h, 1dh 0h, 0h, 0h, 0h bswwi[2:0] 80h 0fh, 14h 19h, 1eh 0h, 0h, 0h, 0h bshwi[3:0]
19/49 stv9937 window specifications 3.7 window display priority management the osd windows are displayed with the following priority: window 4 (top), 3, 2 and 1 (bottom). this order of priority is shown the example given in figure 8 . figure 7: illustration of window bordering and shadowing effects figure 8: example of window displays m pixels n scan lines m pixels n scan lines window bordering window shadowing window 1 hd vd window 2 window 3 window 4 screen axis origin
character specifications stv9937 20/49 4 character specifications 4.1 general description there are: 496 monochrome characters and 16 multi-color characters in rom 32 to 127 characters per line character height varies between 18 and 127 scan lines 0 to 62 scan space lines between character rows, with the same number of lines above and below the rows of characters. with the possibility to select: blinking effect for each character shadowing effect for characters in each window background and foreground character colors: for each character, among a color-shop of 8 color-boxes per window. there is a color-shop for each window. the color-boxes define the background colors and the foreground character colors and blinking effect. 4.2 horizontal resolution the horizontal resolution defines the number of pixels per line expressed in characters unit. this value is selected by bits hr[6:0]. the range of the horizontal resolution is from 32 to 127 characters, in steps of one character each. the default value is 32 characters per line (20h). if bits hr[6:0] are programmed with a value less than 32, the horizontal resolution will be 32 characters per line (minimum value). hr[6:0] = number of characters per line it is important that the maximum pixel frequency must be respected (clk2= 120 mhz maximum). as each character is 12 pixels long, the number of pixels per line varies from 384 to 1524. for more information, refer to section 6: pixel clock generator on page 29 . 4.3 character height the vertical height defines the number of scan lines used to display the characters. this value is selected by bits ch[6:0]. table 19: horizontal resolution fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 01h 20h hr[6:0] table 20: vertical character height fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 02h 12h ch[6:0]
21/49 stv9937 character specifications the range of the vertical height is from 18 to 127 lines. ch[6:0] = number of scan lines used to display the characters the characters stored in rom are coded on 18 lines. if bits ch[6:0] are programmed with a value less than 18, the characters will be automatically displayed with a height of 18 scan lines (minimum value). when a multiple of 18 scan lines are displayed, all rom lines are repeated n number of times, with n in the range of 1 to 7, so as not to exceed the display of 127 scan lines. for example, if ch[6:0] = 36, each rom line is repeated twice. if the number of scan lines displayed is not a multiple of 18, certain rom lines are repeated more often than others, as shown in ta bl e 2 1 . for example, if ch[6:0] = 40, each rom line is repeated twice and rom lines 3, 7, 10 and 14 are repeated three times. ta bl e 2 1 shows which rom lines, from 0 to 17, are repeated depending on the ch[6:0] value. 4.4 space lines the space lines define the number of scan lines above and below each character row. this value is selected by bits rspa[4:0]. the total row height is defined as follows: row_height = character_height + 2 x space_lines (see figure 9 ) table 21: repeated rom lines 1 1. ?r? = repeated rom lines ?a? = number of additional repeated lines ch value a01234567891011121314151617 18, 36, 54, 72, 90, 108, 126 0 19, 37, 55, 73, 91, 109, 127 1 r 20, 38, 56, 74, 92 ,110, 2 r r 21, 39, 57, 75, 93, 111 3 r r r 22, 40, 58, 76, 94, 112 4 r r r r 23, 41, 59, 77, 95, 113 5 r r r r r 24, 42, 60, 78, 96, 1146rrrrrr 25, 43, 61, 79, 97, 115 7 r r r r r r r 26, 44, 62, 80, 98, 116 8 r r r r r r r r 27, 45, 63, 81, 99, 117 9 r r r r r r r r r 28, 46 ,64, 82, 100, 118 10 r r r r r r r r r r 29, 47, 65, 83, 101, 119 11 r r r r r r r r r r r 30, 48, 66, 84, 102, 120 12 r r r r r r r r r r r r 31, 49, 67, 85, 103, 121 13 r r r r r r r r r r r r r 32, 50, 68, 86, 104, 122 14 r r r r r r r r r r r r r r 33, 51, 69, 87, 105, 123 15 r r r r r r r r r r r r r r r 34, 52, 70, 88, 106, 124 16 rrrrrrrrrrrrrrrr 35, 53, 71, 89, 107, 125 17 rrrrrrrrrrrrrrrrr
character specifications stv9937 22/49 the range of spacing lines is from 0 to 31 scan lines, in steps of one scan line each. the default value is 0 scan lines. the space lines are displayed in the color of the associated character background. 4.5 character colors the colors for the characters, character background and blinking effect is separately programmable for each osd window. the color values are stored in a color-shop of 8 color-boxes for each window. there are 4 color-shops, 1 per window, offering the user 32 possibilities of character coloring. as the color-boxes are in ram, the user must write to the color-box prior to using it. color-box data is stored in window 0, row 2. for more information, refer to section 2.4: addressing map on page 12 . 4.5.1 character background color a character background color can be separately programmed for each of the color-boxes. this value is selected by bits bc, br, bg and bb. for more information concerning the window background color, refer to section 3.5: window background color . bit bc is used to define if a specific character background color will be displayed or if the character background color is the color of the window background. table 22: row height (space lines) fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 03h 0h rspa[4:0] figure 9: row height definition table 23: color-box fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 82h 00h to 1fh bc br bg bb blink fr fg fb a b total row height rspa[4:0] space lines ch[6:0] character height rspa[4:0] space lines
23/49 stv9937 character specifications if a specific character background color is selected for a color-box, the character background color is selected by bits br, bg and bb. . 4.5.2 character color a character color can be separately programmed for each of the color-boxes. this value is selected by bits fr, fg and fb. table 24: character background color color bc br bg bb black 1000 blue 1001 green 1010 cyan 1011 red 1100 magenta 1101 yellow 1110 white 1111 window background color 1 1. see ta b l e 2 5 0 table 25: background color priority bc ti background color 1 x character background color (br, bg and bb) 0 0 window background color (rgbwi) 0 1 transparent background (video active) table 26: character colors color fr fg fb black 000 blue 001 green 010 cyan 011 red 100 magenta 1 0 1 yellow 110 white 111
character specifications stv9937 24/49 4.5.3 character blinking effect a character blinking effect can be separately programmed for each of the color-boxes. this value is selected by the blink bit. when this bit is set to 1, the blinking effect is enabled and the characters blink. 4.6 character shadowing a character shadowing effect can be separately programmed for each of the color-boxes. this value is selected by bits csha[3:0], respectively. the shadowing color is black. when this bit is set to 1, the characters of the corresponding osd window are displayed with a shadowing effect, as shown in figure 10 . the default value is 0 (no shadowing effect). figure 10: character shadowing table 27: character shadowing fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 08h 0h csha[3:0]
25/49 stv9937 character specifications 4.7 character font figure 11 shows the available character font stored in rom. figure 11: character fonts 0 1 2 3 4 5 6 7 8 9 a b c d e 1e 1f 0123456789abcd ef f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d
ram specification stv9937 26/49 5 ram specification 5.1 character coding each character to display is coded with 12 bits in the ram with the following addressing method: character code: bits rc[8:0] are used to address the rom code color code: bits cb[2:0] are used to select 1 of the 8 color-boxes in the color shop of the corresponding osd window. 5.2 window memory allocation the 4 osd windows can be distributed differently. but the displayable windows will always contain a total of 20 blocks (1 block consists of 32 characters). 5.3 memory size allocation the total number of characters or spaces is up to 640 with a maximum window size of 16 rows of 32 characters. the character codes of each window are allocated to a specific memory space. this memory space is programmable for each window. the window size must be less than or equal to its memory allocation. any window size can be modified within its specific memory space, the other windows are not affected by this operation. table 28: character coding fwr fac bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 see table 3 cb[2:0] rc[8:0] figure 12: window memory space window 0 color-boxes 10 blocks 4 blocks 3 blocks 3 blocks 1 block window 1 window 2 window 3 window 4 displayable windows
27/49 stv9937 ram specification the user must reserve a memory space for the largest window. according to the example shown in figure 6 , the total number of characters/spaces are: for example, to change the size of window 3 from 3 rows of 6 characters to 5 rows of 4 characters, the resulting size is 20 characters. the number of rows increases and the number of characters per row decreases. the required memory is at least 20 characters. note: a space is considered as being a character. the memory allocation is made by blocks of 32 characters. the maximum size of a window is 16 rows of 32 characters, or 512 characters. this corresponds to 16 blocks of 32 characters. 1 block is reserved for the color-boxes (see chapter 4: character specifications on page 20 ), leaving 20 blocks of 32 characters for character codes (640 characters maximum). the ram allocation for each window is coded in bits alwi[3:0]. window 4 memory allocation uses the remaining memory space. the number of memory blocks allocated for window ?i? is (alwi +1), the range of allocation is 1 to 16 blocks of 32 characters. the total number of blocks is 20. note: if the user changes only 1 window allocation, the ram addresses of the following windows change. consequently we advise you to write the allocation when the windows are not displayed to avoid false images. table 29: window sizes window size window 1 28 window 2 20 window 3 18 window 4 16 total 82 table 30: window ram allocation fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 09h 39h alw2[3:0] alw1[3:0] 80h 0ah 2h alw3[3:0]
ram specification stv9937 28/49 the default window ram allocations are listed in ta bl e 3 1 . window 1: 10 blocks of 32 words = 320 characters (alw1 = 9). window 2: 4 blocks of 32 words = 128 characters (alw2 = 3). window 3: 3 blocks of 32 words = 96 characters (alw3 = 2). window 4: the remaining ram (3 blocks = 96 characters). 5.4 window reset all the ram data from one of the four osd windows can be reset by writing to bits resetw[3:0]. when the resetw bit is set to 1, all the ram data in the allocation memory space of the corresponding osd window is reset. these bits are automatically cleared when the ram allocation reset is finished. table 31: window ram default values alwi default description alw1 9h 320 characters (10 blocks) alw2 3h 128 characters (4 blocks) alw3 2h 96 characters (3 blocks) table 32: ram allocation enable and reset fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 0bh 0h resetw[3:0]
29/49 stv9937 pixel clock generator 6 pixel clock generator the pixel clock generator is used to synchronize the display clock with the horizontal synchronisation (hsync) signal. this generator is based on a pll function used to perform correct jitter. the pixel frequency is defined with the horizontal line frequency and the horizontal resolution. pixel frequency (f pixel2 ) = 12 x hr[6:0] x f hline the vco[1:0] value is used to select the appropriate curve partition of the vco. the pll generates: a pixel clock for the osd from 7.68 mhz to 120 mhz: f pixel2 a pixel clock for the pictureboost tm (pb) from 30 to 60 mhz: f pixel1 . the pictureboost tm pixel clock provides the resolution of the pb pixel.it is locked on the hsync signal and the referenced edge is programmed using the hsp bit. when the monitor resolution is changing, the micro controller changes the osd horizontal resolution to adapt the width of the osd window. in this case, the frequency of the pb clock is changing also. so the width and the position and the resolution of the pb window is changing. table 33: vco curve partition vco value (binary) vco curve partition 00 7.68 mhz < f pixel2 < 15 mhz (default value) 01 15 mhz < f pixel2 < 30 mhz 10 30 mhz < f pixel2 < 60 mhz 11 60 mhz < f pixel2 < 120 mhz table 34: vco range fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 00h 0h vco[1:0]
picture boosttm stv9937 30/49 7picture boost tm picture boost tm allows images to be boosted either within a window, a screen area or over the entire screen. to perform this function, the stv9212 preamplifier is required as well as the picture boost tm software which sends the window or screen area coordinates (x1, x2,y1,y2) to the rgb video channels. the picture boost tm system embedded in the stv9937 includes: the rgb comparator the coordinate decoder the control and data registers the stv9937 computes the data received on the rgb channel and generates a boost signal which is then sent to the stv9212. the coordinates can be received through the i2c bus by the mcu as well. the stv9937 also includes three 8 bits register used to store data received by rgb. 7.1 video rgb input stage the input stage is a triple analog-digital buffer for the video rgb inputs. the input voltage range is 0 to 0.7 v the inputs have to be supplied through a serial capacitor (100nf) the input rgb must be set to ?0? during the horizontal sync. the input stage includes a clamping function using the hsync signal to fix the dc level of inputs. the input stage is configured by three control bits; thctl, clp and encl as shown in figure 37 . figure 13: hsync clamping function thtcl encl hsync clp and 100nf
31/49 stv9937 picture boosttm 7.2 pictureboost tm rgb decoder the stv9937 can receive the coordinates of the area to boost through the rgb channel or through i2c bus. the picture boost tm area coordinates are coded as follows: 7.2.1 data sent using i2c before sending data to the corresponding registers, the pbvm bit must be set to 1. then the coordinates can be sent to the corresponding address, see ta bl e 3 6 : row 1, col 3 to 6 for x1, x2 coordinates row 1, col 7 to 10 for the y1, y2 coordinates. 7.2.2 data sent using the rgb channel the picture boost tm software sends coordinate data through the rgb channel: the red channel contains the x1, x2 and y1, y2 coordinates information the green channel contains a specific activation code the blue channel contains the clock signal. the decoder stores the coordinates values to the corresponding address: row 1, col 3 to 6 for x1, x2 coordinates row 1, col 7 to 10 for the y1, y2 coordinates. x1 and x2 are referred to the hsync signal, the resolution is f pixel1 (from 30 mhz to 60 mhz) table 35: pictureboost tm window coordinates bits description x1[12:0] left coordinate of the window, in clk1 pixels (f pixel1 ) x2[12:0] right coordinate of the window, in clk1 pixels y1[10:0] top coordinate of the window, in lines y2[10:0] bottom coordinate of the window, in lines
picture boosttm stv9937 32/49 in the same way, 3 other 8 bits of register data(d3a, d3b and d3c)can be sent via the video rgb and detected by the stv9937. these three registers can be read by the i2c bus at row1, col 11 to 13. this specific data cannot be written by i2c. figure 14: pictureboost tm area coordinates screen window 3 (x 1 , y 1 ) (x 2 , y 2 ) h sync v sync boosted area y 1 y 2 x 1 x 2
33/49 stv9937 picture boosttm 7.3 control registers description table 36: control registers pb: window 0, w[2:0] = ?000?, row = 1 r[3:0] =?0001? address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 row col. 1 0 thctl clp encl hflyp osdref reserved enpb 1 1 reserved reserved pbvm pbon 1 2 offsetlin[1:0] offsetpix[5:0] 13 x1[12:8] 14 x1[7:0] 15 x2[12:8] 16 x2[7:0] 17 y1[10:8] 18 y1[7:0] 19 y2[10:8] 1a y2[7:0] 1 b d3a[7:0] 1 c d3b[7:0] 1d d3c[7:0] 1e reserved 1f reserved 1 1x reserved 11fhmux 0 0 0 0 0 0 0 table 37: pictureboost tm configuration bit description thctl the thctl bit selects the thresholds of the input voltage (low or high) 0: low thresholds selected 1: high thresholds selected (default value) clp the clp bit selects the polarity of the hsync signal for the clamp 0: clamp when hsync = 1 (default value) 1: clamp when hsync = 0 encl the encl bit enables the clamping function for the rgb input stage 0: clamping disabled 1: clamping enabled (default value)
picture boosttm stv9937 34/49 7.4 line and pixel offsets due to the intrinsic delay on the rgb channel during the rgb decoding, 2 offsets can be applied for fine tuning as shown in below: note:it is recommended to adjust the pixel offset each time the monitor resolution changes. 7.5 pll synchronised the stv9937 pll can either be synchronized on the hfly or hsync signals. warning:once synchronized on hfly, the picture boost tm feature cannot be guaranteed. hflyp the hflyp bit configures the polarity of the hfly signal 0: falling edge active (default value) 1: rising edge active osdref the osdref selects the signal taken as reference 0: hfly is the reference (default value) 1: hsync is the reference enpb the enpb bit selects picture boost tm decoding 0: the rgb video inputs are not decoded, there is no possibility of displaying the pb. the user can write x1/x2 y1/y2 coordinates in the registers, but the on/off bit is inactive (default value) 1: pb decoding is active and the pb display can be made active with the pbon bit pbon the pbon bit selects picture boost tm display 0: pb is not displayed (default value) 1: pb is displayed on the screen with the coordinates written in the x/y registers pbvm the pbvm bit selects the picture boost tm interface 0: interface via rgb (default value) 1: interface via i2c bits description offsetlin[1:0] the line offset in signed radix is coded on 2 bits from -2 to +1. default value is 0. offsetpix[5:0] the pixel offset in signed radix is coded on 6 bits from -32 to +31. default value is 0. bit description hmux 0: hsync is the synchronization signal 1: hfly is the synchronization signal table 37: pictureboost tm configuration bit description
35/49 stv9937 general osd programming 8 general osd programming 8.1 enable osd the osd window displays are enabled by the enosd bit. enosd = 1: osd window displays are active. enosd = 0: osd window displays are inactive. pin fblk = 0 and pins rout, gout and bout pins = 0 (bit rgbpol is 0). the default value is 0. 8.2 fade-in and fade-out effect the fade-in and fade-out effect is used to progressively increase/decrease the osd window to/ from its full size. this effect is enabled by the fade bit. fade = 1: fade effect is active fade = 0: fade effect is inactive (default value) 8.3 full screen display the stv9937 allows a full screen display with a selectable color programmable by the fbk bit as follows: fbk = 1: the video area is replaced by the color coded in bits fsr, fsg and fsb (full screen color values). pin fblk is always 1. fbk = 0: normal video mode whether or not the osd menu is displayed. the default value of bit fbk is 0. table 38: enable osd fwr fac bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 00h enosd table 39: fade fwr fac bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 00h fade table 40: full screen registers fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 01h 0h fbk 80h 03h 0h fsr fsg fsb table 41: full screen colors color fsr fsg fsb black (default value) 0 0 0 blue 001 green 010
general osd programming stv9937 36/49 8.4 signal polarity and triggering vertical sync triggering (vs input) the active edge of the vs pin used for vertical synchronization is selected by bit vsp. vsp = 0: the falling edge is active. (default value) vsp = 1: the rising edge is active. horizontal sync triggering (hsync input) the active edge of the hsync pin used for horizontal synchronization is selected by bit hsp. hsp = 0: the falling edge is active. (default value) hsp = 1: the rising edge is active. rgb output polarity (rout, gout and bout outputs) the output polarity of pins rout, gout and bout is selected by bit rgbpol. rgbpol = 0: rgb active at 1 (default value) rgbpol = 1: rgb active at 0 cyan 011 red 100 magenta 1 0 1 yellow 110 white 111 table 42: signal polarity fwr fac default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80 00 fbkpol rgbpol vsp hsp table 43: rgb output control enosd bit rgbpol bit rgb outputs display 1 0 active at 1 osd 1 1 active at 0 osd 00000video 01111video table 41: full screen colors (continued) color fsr fsg fsb
37/49 stv9937 general osd programming fast blanking output polarity (fblk output) the output polarity of the fblk pin is selected by bit fblkpol. the default value is 0. 8.5 reset power on reset the digital core and the pll are asynchronously reset at power on. soft reset a soft reset is enabled by the rst bit. rst = 1: the digital core is reset. all control registers including pictureboost tm but with the exception of pll registers, are reset at the same value as at power on reset. it is not necessary to write rst = 0 to stop the reset. this bit is automatically cleared. pll register reset the pixel clock generator (vco[1:0]) and horizontal resolution (hr[6:0]) bits are reset by the rst_pll bit. rst_pll = 1: hr[6:0] and vco[1:0] are reset to the same value as the power-on reset. it is not necessary to write rst_pll = 0 to stop the reset. this bit is automatically cleared. table 44: fast blanking output polarity selection fblkpol description 0 when osd display, fblk = 1 when active video, fblk = 0 1 when osd display, fblk = 0 when active video, fblk = 1 table 45: fblk output control enosd bit fblkpol bit fbk bit fblk output display 1000video default value 1001osd 1011osdfull screen 1100osd fblk inverted 1101video 1110osdfull screen 0 0 x 0 video no osd 0 1 x 1 video no osd table 46: reset fwr fac bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 06h rst_pll rst
registers stv9937 38/49 9registers 9.1 register specification control registers are located at address in window 0, row 0 and row 1. color-boxes are located at addresses in window 0, row 2. see section 4.5 on page 22 . character codes are located at addresses in windows 1 to 4, as described in section 5.1 on page 26 . table 47: non-displayable window register mapping register window row fwr code osd control registers 0 0 80h pictureboost tm control registers 0 1 81h color-box registers 0 2 82h
39/49 stv9937 registers table 48: control registers: window 0, row = 0 fwr fac col default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h 00h 0h 0h fbkpol = 0 rgbpol = 0 fade = 0 enosd = 0 vsp = 0 hsp = 0 vco[1:0] = 00 80h 01h 1h 20h fbk = 0 hr[6:0] :horizontal resolution = 32 characters 80h 02h 2h 12h ch[6:0] = character height = 18 80h 03h 3h 0h full screen rgb = fs rgb = 000 rspa[4:0] = row spacing = 0 80h 04h 4h 0h hd[6:0] = horizontal delay reference = 0 (50 pixels) 80h 05h 5h 0h vd[7:0] = vertical delay reference = 0 (2 lines) 80h 06h 6h 0h rst_pll = 0 rst = 0 80h 07h 7h 0h enbs4/3/2/1 = 0000 enw4/3/2/1 = 0000 80h 08h 8h 0h csha[3:0] = 0 80h 09h 9h 39h alw2[3:0] = 3 (4 blocks = 128 characters) alw1[3:0] = 9 (10 blocks = 320 characters) 80h 0ah ah 2h alw3[3:0] = 2 (3 blocks, 96 characters) 80h 0bh bh 0h resetw[3:0] = 0000 80h 0ch ch 0h hdw1[6:0] = 0 80h 0dh dh 0h vdw1[5:0] = 0 80h 0eh eh 19h bsww1[2:0] = 000 hsw1[4:0] = 25 (26 characters) 80h 0fh fh bh bshw1[3:0] = 0000 vsw1[3:0] = 11 (12 rows of characters) 80h 10h 10h 7h ws rgb 1 = 000 : black bsw1 =0 t1 = 0 rgb w1 = 111:white 80h 11h 11h 20h hdw2[6:0] = 32 80h 12h 12h 0h vdw2[5:0] = 0 80h 13h 13h 9h bsww2[2:0] = 000 hsw2[4:0] = 9 (10 characters) 80h 14h 14h 4h bshw2[3:0] = 0000 vsw2[3:0] =4 (5 rows of characters) 80h 15h 15h 7h ws rgb 2 = 000 : black bsw2 =0 t2 = 0 rgb w2 = 111:white 80h 16h 16h 0h hdw3[6:0] = 0 80h 17h 17h ch vdw3[5:0] =12 80h 18h 18h fh bsww3[2:0] = 000 hsw3[4:0] = 15 (16 characters) 80h 19h 19h 7h bshw3[3:0] = 0000 vsw3[3:0] = 7 (8 rows of characters) 80h 1ah 1ah 7h ws rgb 3 = 000 : black bsw3 =0 t3 = 0 rgb w3 = 111:white 80h 1bh 1bh 10h hdw4[6:0] = 16 80h 1ch 1ch ch vdw4[5:0] = 12 80h 1dh 1dh fh bsww4[2:0] = 000 hsw4[4:0] = 15 (16 characters) 80h 1eh 1eh 7h bshw4[3:0] = 0000 vsw4[3:0] = 7 (8 rows of characters) 80h 1fh 1fh 7h ws rgb 4 = 000 : black bsw4 =0 t4 = 0 rgb w4 = 111:white
registers stv9937 40/49 table 49: control registers: window 0, row = 1 fwr fac col default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 81h 00h 0h 50h 0 thctl = 1 clp = 0 encl = 1 hflyp = 0 osdref = 0 0 enpb = 0 81h 01h 1h 4h 0 1 pbvm = 0 pbon = 0 81h 02h 2h 0h offsetlin[1:0] offsetpix[5:0] 81h 03h 3h 0h x1[12:8] 81h 04h 4h 0h x1[7:0] 81h 05h 5h 0h x2[12:8] 81h 06h 6h 0h x2[7:0] 81h 07h 7h 0h y1[10:8] 81h 08h 8h 0h y1[7:0] 81h 09h 9h 0h y2[10:8] 81h 0ah ah 0h y2[7:0] 81h 0bh bh 0h d3a[7:0] 81h 0ch ch 0h d3b[7:0] 81h 0dh dh 0h d3c[7:0] 81h 0eh eh 0h reserved 81h 0fh fh 0h reserved 81h 1xh 1xh 0h reserved 81h 1fh 1fh 0h hmux = 0 0 0 0 0 0 0 0
41/49 stv9937 registers table 50: color registers: window 0, row = 2 fwr fac col bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 82h 00h 0h window1 color-box 1: bc- br-bg-bb-blink-fr-fg-fb 82h 01h 1h window1 color-box 2: bc- br-bg-bb-blink-fr-fg-fb 82h 02h 2h window1 color-box 3: bc- br-bg-bb-blink-fr-fg-fb 82h 03h 3h window1 color-box 4: bc- br-bg-bb-blink-fr-fg-fb 82h 04h 4h window1 color-box 5: bc- br-bg-bb-blink-fr-fg-fb 82h 05h 5h window1 color-box 6: bc- br-bg-bb-blink-fr-fg-fb 82h 06h 6h window1 color-box 7: bc- br-bg-bb-blink-fr-fg-fb 82h 07h 7h window1 color-box 8: bc- br-bg-bb-blink-fr-fg-fb 82h 08h 8h window2 color-box 1: bc- br-bg-bb-blink-fr-fg-fb 82h 09h 9h window2 color-box 2: bc- br-bg-bb-blink-fr-fg-fb 82h 1ah ah window2 color-box 3: bc- br-bg-bb-blink-fr-fg-fb 82h 1bh bh window2 color-box 4: bc- br-bg-bb-blink-fr-fg-fb 82h 1ch ch window2 color-box 5: bc- br-bg-bb-blink-fr-fg-fb 82h 1dh dh window2 color-box 6: bc- br-bg-bb-blink-fr-fg-fb 82h 1eh eh window2 color-box 7: bc- br-bg-bb-blink-fr-fg-fb 82h 1fh fh window2 color-box 8: bc- br-bg-bb-blink-fr-fg-fb 82h 10h 10h window3 color-box 1: bc- br-bg-bb-blink-fr-fg-fb 82h 11h 11h window3 color-box 2: bc- br-bg-bb-blink-fr-fg-fb 82h 12h 12h window3 color-box 3: bc- br-bg-bb-blink-fr-fg-fb 82h 13h 13h window3 color-box 4: bc- br-bg-bb-blink-fr-fg-fb 82h 14h 14h window3 color-box 5: bc- br-bg-bb-blink-fr-fg-fb 82h 15h 15h window3 color-box 6: bc- br-bg-bb-blink-fr-fg-fb 82h 16h 16h window3 color-box 7: bc- br-bg-bb-blink-fr-fg-fb 82h 17h 17h window3 color-box 8: bc- br-bg-bb-blink-fr-fg-fb 82h 18h 18h window4 color-box 1: bc- br-bg-bb-blink-fr-fg-fb 82h 19h 19h window4 color-box 2: bc- br-bg-bb-blink-fr-fg-fb 82h 1ah 1ah window4 color-box 3: bc- br-bg-bb-blink-fr-fg-fb 82h 1bh 1bh window4 color-box 4: bc- br-bg-bb-blink-fr-fg-fb 82h 1ch 1ch window4 color-box 5: bc- br-bg-bb-blink-fr-fg-fb 82h 1dh 1dh window4 color-box 6: bc- br-bg-bb-blink-fr-fg-fb 82h 1eh 1eh window4 color-box 7: bc- br-bg-bb-blink-fr-fg-fb 82h 1fh 1fh window4 color-box 8: bc- br-bg-bb-blink-fr-fg-fb
application hints stv9937 42/49 10 application hints 10.1 software hints 10.1.1 programming recommendations 1. write a new allocation just before the ram reset. 2. write a new allocation at any time but take care of the window display. 3. when resetting the ram and writing in it just after, write in the ram respecting the same order as the reset: from the first to the last reset window, from the first window address (row 0, col 0) to the last, incrementing columns, then rows, then windows. 4. define the window horizontal size prior to writing character and color codes in ram. hswi is used to compute the ram address. 10.1.2 examples of programming it is recommended to program the stv9937 in the following sequence: via rgb video mode ? set enpb =1 ? send data via rgb video: y then x coordinates. via i2c mode ? set enpb =1, pbvm=1, pbon =0 ? send data via i2c: x and y coordinates. ? set pbon =1 changing the mode ? set pbon = 0 ? change pbvm bit ? write new coordinates, then the pbon can be set to 1. hard reset at power-up (following a power-up) 1. write window 0 registers to set the osd parameters: write ? vco[1:0], horizontal resolution and vertical height of characters, ? the position of reference, ? the allocations if they are incorrect (by default: 320 characters for window 1, 128 characters for each of the others windows) ? the windows position and size, ? the color-boxes that will be used. 2. write the character codes for each window to display. 3. write the color-box data for each window to display. 4. write the enable of windows: enwi = 1 then enosd=1. change of position & size of 1 window (ex. window 3) without disable of window 1. write new position and sizes. 2. write new characters in the ram.
43/49 stv9937 application hints re-allocation, reset, and writing new characters in windows 1. disable windows. 2. write new allocations. 3. reset the windows. 4. write new positions and sizes in control registers. 5. write new color-boxes. 6. write new characters and color-box data. 7. enable windows. 10.2 hardware hints the serial resistors on the rout, gout, bout, fblk and pb outputs must be as close as possible to the device. both decoupling capacitors (100 nf and 100 f) must be as close as possible to the analog (pin 13) and digital (pin5) power supplies (see figure 15 ). pll network must be close to the device but far from the rout, gout, bout, fblk and pb outputs. pll network and rout, gout, bout and fblk outputs should be separated by the avdd 3.3 v power trace. pll ground (agnd) should not be connected either to dvss or to other grounds of the videoboard, as the ground is already connected internally. it is better to supply the stv9937 device through ferrite beads (as an example the ferrite bead could be 742 760 5 type from wrth electronik) instead of traditional inductance that could damage the osd jitter with some parasitic resonance.
application diagrams stv9937 44/49 11 application diagrams figure 15: stv9937 application diagram blk/hfly hs sda scl vs 3.3v 3.3v from video connector to the pre-amplifier r38 68k r42 330r r41 330r c36 100nf c33 100nf u3 stv9937 avss 1 rp 2 vco 3 avdd 4 test 1 5 test 2 6 hfly 7 vs 8 hsync 9 sda 10 scl 11 nc 12 ivss 24 bin 23 gin 22 rin 21 ivdd 20 dvdd 19 dvss 18 pb 17 bout 16 gout 15 rout 14 fblk 13 r37 100r r39 100r r3 3m3 c37 100uf/25v c38 100nf c34 100nf r40 330r r43 330r fb1 bead_coil c30 560pf r46 330r r32 100r r35 9k1 fb2 bead_coil c1 47pf c35 100uf/25v c32 100nf r34 100r
45/49 stv9937 electrical and timing characteristics 12 electrical and timing characteristics 12.1 absolute maximum ratings 12.2 operating conditions 12.3 electrical and timing characteristics (v dd = 3.3v, v ss = 0v, t a = 0 to 70 o , unless otherwise specified) symbol parameter value unit av dd , iv dd , dv dd , ov dd dc supply voltage -0.5, +4.0 v v in input voltage for scl, sda, vs, hfly and hsync -0.5, 5.5 v t oper ambient operating temperature 0, +70 o c t stg storage temperature -40, +125 o c symbol parameter min. typ. max. unit vdd dc supply voltage av dd , iv dd , dv dd , ov dd. 3.0 3.3 3.6 v t oper ambient operating temperature 0 25 70 o c symbol parameter min. typ. max. unit electrical characteristics idd analog and digital supply current ai dd + di dd + oi dd 50 ma v il input low voltage (scl, sda, vs, hfly, hsync, test1 and test2 pins) 0.8 v rin, gin, bin (video input voltage amplitude) 1 1. for pictureboost data transmission only 050mv v ih input high voltage (scl, sda, vs, hfly and hsync pins) test inputs are connected to ground 2.0 5.0 v rin, gin, bin (video input voltage amplitude) 1 0.5 0.7 1.0 v v ol rout, gout, bout, fblk and pb output low voltage (i ol = 3 ma) 0.4 v sda open drain output low voltage (i ol = 4 ma) 0.4 v v oh rout, gout, bout, fblk and pb output high voltage (i oh = 3 ma) 2.4 - v sda open drain output high voltage, pulled up by external 3v to 5v power supply 5.0 v timing characteristics freq (hline) horizontal synchronization input range 150 khz t r rout, gout, bout, fblk and pb output rise time (c load = 15 pf) 2ns t f rout, gout, bout, fblk and pb output fall time (c load = 15 pf) 2ns
electrical and timing characteristics stv9937 46/49 12.4 i2c bus characteristics table 51: characteristics of the sda an scl bus lines for f/s-mode i2c-bus devices symbol parameter standard mode fast mode unit min. max. min. max. i2c interface: sda and scl t sp pulse width of spikes which must be suppressed by the input filter n/a n/a 0 50 ns f scl scl clock frequency 0 100 0 400 khz t hd;sta hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0 0.6 s t low low period of the scl clock 4.7 1.3 s t high high period of the scl clock 4.0 0.6 s t su; t sta set-up time for a repeated start condition 4.7 0.6 s t hd;dat data hold time 0 3.45 0 0.9 s t su;dat data set-up time 250 100 ns t r rise time of both scl and sda signals 1000 20 + 0.1c b 300 ns t f fall time of both scl and sda signals 300 20 + 0.1c b 300 ns t su; t sto set-up time for stop condition 4.0 0.6 s t buf bus free time between a stop and a start condition 4.7 1.3 s c b capacitive load for each bus line 400 400 pf figure 16: definition of timing for f/s-modes handbook, full page width s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f sda scl p s t buf t r t f t r t sp t hd;sta
47/49 stv9937 package mechanical data 13 package mechanical data figure 17: 24-pin plastic dual in-line shrink package table 52: pdip24s package dim. mm inches min. typ. max. min. typ. max. a 5.08 0.200 a1 0.51 0.020 a2 3.05 3.30 4.57 0.120 0.130 0.180 b 0.38 0.46 0.56 0.015 0.018 0.022 b2 0.89 1.02 1.14 0.035 0.040 0.045 c 0.23 0.25 0.38 0.009 0.010 0.015 d 22.35 22.61 22.86 0.880 0.890 0.900 e 7.62 8.64 0.300 0.340 e1 6.10 6.40 6.86 0.240 0.252 0.270 e 1.78 0.070 ea 7.62 0.300 eb 10.92 0.430 ec 0.00 1.52 0.000 0.060 l 2.54 3.30 3.81 0.100 0.130 0.150 number of pins n 24 stand -o ff be b2 d 13 12 24 1 ea c e1 e eb eb ec e l a a2 a1 e1 0.15 in. gage plane 0.38 mm.
revision history stv9937 48/49 14 revision history table 53: summary of modifications date version description 20 february 2003 0.1 first draft. 22 may 2003 0.2 general modifications, corrections and updates. 26 june 2003 0.3 removal of draft status. 08 july 2003 0.4 update to figure 3: pictureboosttm system block diagram on page 6 . 24 september 2003 0.5 updated section 10.2: hardware hints on page 43 and figure 15: stv9937 application diagram on page 44 . 20 january 2004 0.5 pll synchronization information added.
49/49 stv9937 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwi se under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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